7497: Binary Rate Multiplier (Base 64)

This is a specialized TTL package. For every 64 clock-input pulses, a selected number of 0-through-63 output pulses are provided.

For normal operation, ground the Strobe, Clear, and Enable lines. Make the Cascade input positive. Apply a square wave to the Clock input. At the Enable output you will have a 1-of-64 decoding of the input clock, i.e., one pulse for every 64 clock-input pulses.

At the normal output (pin 5), you will get as many pulses per 64 input-clock cycles as you select on the Rate inputs. For instance, if R32 is high, R16 is low, R8 is low, R4 is high, R2 is low, and R1 is high, you will get 37 output pulses per one enable-out pulse or 37 output pulses per 64 clock cycles.

In general, the pulses are not evenly spaced as they can occur only coincidentally with a time slot on the input clock. Jitter is inherent in a rate multiplier system.

If the Clear input is made positive, the internal divide-by-64 counter is reset to zero. If the Strobe input is made high, the counter will operate, but no rate pulses will appear at pins 5 or 6. Pin 6 is the complement of pin 5 and is gated by the Cascade input. The Cascade input-low inhibits the output of pin 6. Refer to data sheet for more operation details.

Contents

• Home
• Making a Gottlieb Pinball-Inspired VFD Clock
• Making a Williams Pinball-Inspired Panaplex Clock
• Learn About Logic