7476: Dual JK Level-Triggered Flip-Flop (With Preset and Preclear)

Contains two independent level-clocked JK flip-flops. Note the unusual supply connections.

This is a clocked logic block. There are two outputs: Q, and its complement Q'.

Under certain input conditions Q and Q' can change whenever the Clock input goes to a low level. The Q and Q' outputs do not change for a change in the J and K inputs; the only time they can change is as the input clock goes to a low level.

If J and K are grounded, the clock does nothing. If J and K are made positive, the clock changes the output states on Q and Q', or binarily divides. If J is high and K is low, clocking makes Q high and Q' low. If J is low and K is high, clocking makes Q low and Q' high.

Information on the J and K inputs can be changed only once immediately after clocking. Further changes can bring about invalid operation. The clock must be conditioned to drop very rapidly per desired operation.

The Clear and Set inputs should be left, or tied positive for normal operation. If the Clear input is grounded, the flip-flop immediately goes into the state with Q low and Q' high. If the Set input is grounded, the flip-flop immediately goes into the state with Q high and Q' low. Set and Clear should never be simultaneously grounded, or a disallowed state will result.

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