7475: Quad Latch (Level-Sensitive)
This package contains four memory elements. Note the unusual supply connections.
The memories are controlled in pairs with an Enable control. If the Enable control is high, the memories follow the input, thereby providing the input signal at Q and the complement of the input at Q'. A low at the D input appears as a low at Q and a high at Q'.
For use as a quad storage latch, both Enables are paralleled. Enable-high follows the input. Enable-low holds the previous value.
Note that this is not a clocked system and cannot be used as a shift-register element. Stages cannot be cascaded,
| Pin # | Pin Assignment |
|---|---|
| 1 | Q' 1 |
| 2 | D 1 |
| 3 | D 2 |
| 4 | Enable 3, 4 |
| 5 | Power (+5V) |
| 6 | D 3 |
| 7 | D 4 |
| 8 | Q' 4 |
| 9 | Q 4 |
| 10 | Q 3 |
| 11 | Q' 3 |
| 12 | Ground |
| 13 | Enable 1, 2 |
| 14 | Q' 2 |
| 15 | Q 2 |
| 16 | Q 1 |
Contents