7474: Dual D Edge-Triggered Flip-Flop (With Preset and Preclear)

Contains two independent positive-edge-clocked D flip-flops. This is a clocked logic block. There are two outputs: Q, and its complement Q'.

The information presented to the D input goes on to the Q output whenever the clock input changes from a low to a high level. The only time the output can change is when the clock goes positive; changes on the D input are not passed on if the circuit is not clocked.

If D is high, on clocking, Q goes high and Q' goes low. If D is low, on clocking, Q goes low and Q' goes high.

Information on the D input can be changed at any time. It is only its value at the instant of the positive clock edge that matters; this is what is entered into the flip-flop.

The Clear and Set inputs should be left or tied positive for normal operation. If the Clear input is grounded, the flip-flop immediately goes into the state with Q low and Q' high. If the Set input is grounded, the flip-flop immediately goes into the state with Q high and Q' low. Set and Clear should never be simultaneously grounded or a disallowed state will result.

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