74175: Quad "D" Memory (Edge-Clocked)
There are four separate storage latches, each with normal and complementary output. All latches are simultaneously updated.
Information at the D inputs is entered into the latches on the ground-to-high (positive edge) of the clock command. The only time that information is entered into this package is on the positive edge of the clock.
The Clear input is normally held high. Briefly bringing it to ground will clear the memory, making all Q outputs low and all Q' outputs high.
This is a fully clocked system and can be used as a shift-register element. Stages can be cascaded. Note that there is no "Follow" mode; storage is updated only on the positive-clock edge.
| Pin # | Pin Assignment |
|---|---|
| 1 | Clear |
| 2 | Q 1 |
| 3 | Q' 1 |
| 4 | D 1 |
| 5 | D 2 |
| 6 | Q' 2 |
| 7 | Q 2 |
| 8 | Ground |
| 9 | Clock |
| 10 | Q 3 |
| 11 | Q' 3 |
| 12 | D 3 |
| 13 | D 4 |
| 14 | Q' 4 |
| 15 | Q 4 |
| 16 | Power (+5V) |
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