74167: Decade (÷10) Rate Multiplier

This is a specialized TTL package. For every ten input-clock pulses, a selected number of 0 through 9 output pulses are provided.

For normal operation, ground the Strobe, Clear, and Enable lines. Apply a square wave to the Clock input. At the Enable output, you will have a 1-of-10 decoding of the input clock, i.e., one pulse for every ten input-clock pulses.

At the normal output (pin 5), you will get as many pulses per ten input-clock cycles as you select on the Rate inputs. For instance, if R8 is low, R4 is high, R2 is low and R1 is high, you will get five output pulses per one Enable output pulse or per ten input-clock cycles.

In general the pulses are not evenly spaced as they can occur only coincidentally with a time slot on the input clock. Jitter is inherent in a rate multiplier system.

If the Clear input is made positive, the internal divide-by-10 counter is reset to zero. If the Strobe input is made positive, the counter will operate, but no rate pulses will appear at pins 5 or 6. Pin 6 is the complement of pin 5 and is gated by the Cascade input. The Cascade input-low inhibits the output of pin 6. Refer to data sheet for more operating details.

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