74107: Dual JK Level-Triggered Flip-Flop (With Preclear Only)

Contains two independent, level-clocked JK flip-flops. This is a clocked logic block. There are two outputs: Q, and its complement Q'.

Under certain input conditions, Q and Q' can change whenever the Clock input goes to a low level. The Q and Q' outputs do not change for any change in the J and K inputs; the only time they can change is as the input clock goes to a low level.

If J and K are grounded, the clock does nothing. If J and K are made positive. the clock changes the output states on Q and Q', or divides binarily. If J is high and K is low, clocking makes Q high and Q' low. If J is low and K is high. clocking makes Q low and Q' high.

Information on the J and K inputs can only be changed once immediately after clocking. Further changes can bring about invalid operation. The clock must be conditioned to drop only once and then very rapidly.

The Clear input should be left or tied positive for normal operation, If the Clear input is grounded, the flip-flop immediately goes or stays in the state with the Q output low and the Q' output high.

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